Modeling, simulation, and analysis of fault-tolerant multiprocessor architectures

Date of Award




Degree Name

Doctor of Philosophy (Ph.D.)


Electrical and Computer Engineering

First Committee Member

Borivoje P. Furht - Committee Chair

Second Committee Member

Moiez A. Tapia - Committee Member


With the new generation of very fast microprocessors and support chips, it is now possible to consider the development of new tightly coupled multiprocessor systems. These systems provide high levels of processing power, very fast I/O response, minimum interrupt latency, high levels of availability, and graceful degradation in presence of faults.By measuring the bus utilization and the processing power using simulation and analytical multiprocessor models, the significant impact of having large cache memories on the overall system performance is demonstrated. It also shows a limited increase in the line (block) size for systems with large cache sizes.Analytical and experimental performance measurements for two different styles of processing elements clearly shows that a RISC-based microprocessor outperforms a CISC-based microprocessor by an average factor of three. The memory requirements are also measured, and indicate a very close relationship with the program under analysis.Using the Hybrid Automated Reliability Predictor (HARP) software package from NASA, a family of curves are developed for general multiprocessor configurations. Combinatorial and Markovian models are also developed to illustrate the sensitivity of the models to changes in the number of redundant elements as well as to changes in various reliability and availability system parameters.A case study with the description of two different types of tightly coupled multiprocessor architectures is presented: (1) the N4 CISC-style multiprocessor system, and (2) the C3/FT RISC-style fault-tolerant multiprocessor system. These systems are currently under development by MODCOMP in Fort Lauderdale.


Engineering, Electronics and Electrical

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