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Doctor of Philosophy (PHD)
Electrical and Computer Engineering (Engineering)
Date of Defense
First Committee Member
Michael R. Wang - Committee Chair
Second Committee Member
Zhenhua Jiang - Committee Member
Third Committee Member
Xiaodong Cai - Committee Member
Fourth Committee Member
Moiez Tapia - Committee Member
Fifth Committee Member
Fabrice Manns - Outside Committee Member
Recent advances in computing technology have highlighted deficiencies with electrical interconnections at the motherboard and card-to-backplane levels. The CPU speeds of computing systems are drastically increasing with on-chip local clock speeds expected to approach 6 GHz by 2010. Yet, card-to-backplane communication speeds have been unable to maintain the same pace. At speeds beyond a few gigahertz the implementation of electronic interconnects gets increasingly complex, thus, alternative optical interconnection techniques are being extensively researched to relieve the expected CPU to data bus bottleneck. Despite the advantages afforded by optical interconnects there are still demands for improved packaging, enhanced signal tapping, and reduced cost expenditures. In this dissertation, we present a novel array waveguide evanescent coupling (AWEC) technology for card-to-backplane applications. The interconnection scheme is based on waveguide directional coupling between a backplane waveguide and a flexible waveguide connected to the access card or daughter board. To gain access to the shared bus media, coupling of evanescent waves is exploited to tap optical signals from the backplane waveguide to the corresponding card waveguide. The approach results in the elimination of micro-mirror out of plane deflectors and local waveguide termination obstacles present in other reported optical interconnect schemes. Most importantly, the AWEC method can yield efficient multi-drop bus architectures, not possible through free-space, fiber, or traditional guided wave approaches, that only achieve point-to-point topologies. The AWEC concept for optical interconnection was introduced through coupled mode theory, numerical simulations and BeamPROP aided CAD models. Subsequent experimental waveguide analysis was performed and shown to reasonably agree with the simulation results. Likewise, a high-resolution, cost-effective, and rapid prototyping approach for AWEC fabrication has been formulated. Significantly, when compared to other soft lithographic methods, the novel vacuum assisted microfluidic (VAM) technique results in improved waveguide structures, polymer background residue elimination and lower propagation losses. Moreover, experimental results show that our evanescent coupling approach facilitates high-speed coupling between card and backplane waveguides at speeds of 10 Gbps per channel; currently limited only by our testing electronics. In addition, satisfactory eye diagram performance comparable to that of a conventional fiber link, was also observed for the AWEC, alluding to possible aggregate speeds of 100 Gbps. Similarly, we implemented an elementary AWEC shared bus architecture and demonstrate a microprocessor-to-memory interconnect prototype through the proposed AWEC link. Notably, we expect that the AWEC scheme will be significant for high-speed optical interconnects in advanced computing systems.
Microfluidics; Soft Lithography; Waveguide; Integrated Optics; Optical Backplane
Flores, Angel Steve, "Array Waveguide Evanescent Coupler for Card-to-Backplane Optical Interconnections" (2009). Open Access Dissertations. 269.